Technology Scaling Challenges and Opportunities of Memory Devices
President and COO, SK Hynix
Memory semiconductor has been one of the most critical components of all computing systems for decades. At the same time, it has been considered a fundamental bottleneck in such systems in terms of performance. Technology scaling has improved density, power consumption, performance, and cost of semiconductor devices. As we approach the end of traditional Moore’s Law, performance gain for CPU’s from technology scaling is slowing down, raising questions on scalability of computing system’s performance. In this talk, the importance of memory performance enhancement for computing system’s performance gain will be discussed with using different scenarios. End of traditional geometric scaling for memory devices is not far away from today’s technology. Now is the time to pursue revolutionary path as well as evolutionary path. Among them, changing trends in computing system architecture such as workload-based requirements and hardware optimization is providing a guideline for the direction of future DRAM industry. On the other hand, NAND Flash industry successfully unveiled and commercialized 3D NAND. In this talk, trends and challenges for DRAM and NAND Flash memory scaling will be discussed. Emerging memories such as PCRAM, STT-MRAM, and ReRAM are being ready for adoption in the near future. They are likely to provide significant value to some applications based on their system-level workload, especially in the era of data-centric computing environment. They are unlikely to completely replace DRAM and NAND Flash since there are tradeoffs in terms of performance, capacity, reliability, and cost. For continuous innovation and disruptive technology development in memory industry, collaborative efforts in many different fields such as materials, process, device, circuit design and controller technology are needed.
Dr. Seok-Hee Lee received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1988 and 1990, respectively, and the Ph.D. degree from Stanford University, Stanford, CA, in 2000 all in Materials Science. Since February 2013, he joined SK hynix as Senior Vice President and Head of R&D. From 2014 to 2016, he was Executive Vice President and Head of DRAM product and technology. He is currently President and Chief Operating Officer from January 2017. From 1990 to 1995, he was with the Advanced Semiconductor Development group, Hyundai Electronics (now SK Hynix), Korea, where he worked in the area of gate oxide scaling and reliability. From 2000 to 2010, he was with the Portland Technology Development group, Intel Corporation, where he worked on process integration and yield on Intel’s 130-, 90-, 65-nm, and 32-nm advanced CMOS logic technologies. Dr. Lee has received the Intel Achievement Award three times (Intel’s highest recognition for technical achievement) and 11 Intel Divisional Recognition Awards for his technical achievements in transistor and process development. From 2010 to 2013, he was with the department of electrical engineering in KAIST, Korea, as an associate professor. His main research was on nano-scale devices and fabrication. Professor Lee received the best teaching award in 2011. He was a committee member for CMOS devices and technology subcommittee for 2008-2009 IEDM, the chair for the same subcommittee in 2010 IEDM, Asian arrangement chair for 2011 and 2012 IEDM, and emerging technology chair for 2013 IEDM. He also served International Conference on Solid State Devices and Materials (SSDM) as a steering committee member for 2011-2014 meetings. Recently, he gave a plenary talk at IEDM in 2016.
The world first programmable chip development and linear array DSPs
Dept. of System Design, Tokyo Metropolitan University
Abstract: My talk starts with the brief history of programmable DSP chips and their major applications. Several chips which did not have clear target applications had been soon disappeared. Even if they had clear target, they could not survive when the target itself became the world standardization. An example can be seen in media processors which could not survive when MPEG 2 standard chips appeared. GPGPU can be considered as a programmable processor chip when they are used for the neural signal processing area. I recommend that young researcher should join general neural network architectures, because there are no disturbances of standardization.
After that, my talk starts our programmable DSP processor project, because it was selected as the first programmable DSP chip by IEEE in this year. I will talk about why such a project started. I contributed to only the functional level design as a Communications Lab’s member and other LSI level design was carried out by the LSI division. The chip included only small blocks, since it was 40 years ago. I negotiated to improve processor capability. The resultant functional units are reasonable for me for my ADPCM low bit rate speech codec. I also considered another target application of voice-band data modem, both of which includes adaptive FIR implementation. Hard negotiations among us resulted in the introduction of software controlled three-stage pipeline structure which is the key function of our DSP design. The employment of this function enabled excluding other followers DSP in terms of our applications. Although the standardization activity of ADPCM was completed in 1984, we became the first ITU standard ADPCM codec developer with the collaboration with NEC Transmission Division.
The final talk is concerning about DSP chips for our linear array approach for a video codec implementation by Transmission Divisions. They wanted to have such system in order to sell their Video conference systems as soon as possible. Although ITU started the video codec standardization since 1980, it lasted 9 years. Transmission Division wanted to have software control video processor, in order to replace the software, when the standardization is over, However, the standardization process was suddenly finalized within a year from our shipping of the system. I would like to describe this system, because the system employed SPMD(Single Program, Multiple Data stream) unlike to SIMD approach. SPMD used the same software among element processors, which can include many conditional jumps. One restriction is that the all the processing element has to terminate the processing during frame intervals. I hope this approach contributes neural network implementation.
Takao Nishitani was born in Kobe, Japan on May 31, 1948. He recived the B.S., M.S. and PhD degrees in electronics Engineering from Osaka University in 1971, 1973 and 1992, respectively.
He joined NEC corporation in 1973 and has engaged in research on VLSI signal processors, SOC architectures, ADPCM low bit rate speech coding, MPEG wide band audio and video coding, and so on. He has developed the world first programmable DSP processor. He also introduced realtime low bit rate video programmable DSP chips for linear array processor. He also contributed to establish the ITU G.721 ADPCM standard ADPCM codecs and MPEG-1 MP3 and AAC standards. He became a general manager of Information Systems laboratory, where he managed group of Personal Robotics group and Blue Ray Disc Group in addition to Dignal Signal Processing groups as well as speech and image recognition Groups.
In 2004, he moved to the department of Information Systems Engineering in Kochi University of Technology as a Professor. He moved to Tokyo Metropolitan University (TMU) in 2006 as a professor and retired in 2012. Since then, he became a consultant, a visiting professor of TMU for assisting MS and PhD students and a lecturer of the broadcasting University.
He received the 1989 President Award from Japanese Science and Technology Agency, and 2017 IEEE Pederson Medal Award from Solid State Circuits Society in addition to other 3 awards such as Ohrm technical award, ESTAP award, and Bell Labs President Award. He is co-editor of digital Digital Signal Processing for Multimedia Systems (Mercel Dekker, 1999) and co-author of eight other books.
He is now an IEEE Life Fellow and IEICE Fellow.
Recent R&D Advances in Radio-Frequency Sensors in Thailand
Department of Electrical and Electronic Engineering, Asian University
Abstract: In the near future, Internet of Things (IoT) will be widely applied in our modern daily life through physical items communicating to each other, including machine-to-machine (M2M) communications and person-to-computer (P2C) communications; for example, smart buildings, smart cities and smart energy. To drive the future IoT, smart sensor technologies are mandatory, including wireless sensor networks (WSN) and nanotechnology. Thus, the research and development (R&D) on highly efficient, flexible, compact and low-cost sensors is crucial for future IoT industries. Note that many different types of sensors exist and can be applied for monitoring desired physical and other parameters of interest; for example, electronic sensors based on ultrasonic, near infrared and X-ray, chemical sensors and biological sensors. However, this talk will focus on recent R&D advances in electronic sensors based on radio frequency (RF), called RF sensors, for useful wireless sensing applications in Thailand; for example, agricultural products, civil structures and defense technology. Initially, RF sensors on agricultural products (especially, fruits and grains), RF sensors based on ground penetrating radar (GPR) for detection of explosive devices and RF material sensors for industry applications will be presented to show their useful applications. Subsequently, RF sensors based on the RF-identification (RFID) technology, called RFID sensors, will be discussed in detail by focusing on their identification and sensing capabilities, especially RFID sensors for animal identification and RFID material sensors for construction-material products. The research challenges will be discussed as well.
Dr. Danai Torrungrueng received his B.Eng. degree in electrical engineering from Chulalongkorn University, Bangkok, Thailand, in 1993. He obtained his M.S. and Ph.D. degrees in electrical engineering from The Ohio State University, Ohio, USA in 1996 and 2000, respectively. From 1995 to 2000, he was a Graduate Research Assistant (GRA) in the Department of Electrical Engineering, ElectroScience Laboratory, The Ohio State University. Prior to joining Asian University, he worked as a senior engineer in the USA, involved in research and development of the urban propagation modeling project. At present, he is a professor in the electrical and electronic engineering department in the faculty of engineering and technology at Asian University, Thailand.
In 2000, he won an award in the National URSI Student Paper competition at the 2000 National Radio Science Meeting in Boulder, Colorado. During 2004 to 2009, he invented generalized Smith charts, called T-charts or Meta-Smith charts, for solving several problems associated with conjugately characteristic-impedance transmission lines (CCITLs) and bi-characteristic-impedance transmission lines (BCITLs), including their useful applications in applied electromagnetics. He authored Meta-Smith Charts and Their Potential Applications (Morgan & Claypool, 2010) and Advanced Transmission-Line Modeling in Electromagnetics (Charansanitwong Printing, 2012). His research interests are in the areas of electromagnetic sensors, fast computational electromagnetics, rough surface scattering, propagation modeling, electromagnetic wave theory, microwave theory and techniques and antennas. He is currently a senior member of the IEEE, and a member of the ECTI, where he has served as an ECTI technical chair in electromagnetics since 2014. In addition, he served as a TPC co-chair of TJMW2016, and has currently served as a vice co-chair of TJMW2017 and the TPC chair of ISAP2017. Furthermore, he is a co-founder of the Innovative Electromagnetics Academy of Thailand (iEMAT) founded in 2013 (http://www.iemat.org/).